1. Field of the Invention
The present invention relates generally to testing apparatuses and methods for making functional verification of semiconductor devices, measurement of alternating current characteristics and direct current characteristics of the devices, and the like. More particularly, the invention relates to pin electronics for making electrical connection to pin terminals of a semiconductor device, applying a test signal to the semiconductor device, receiving output signals from the device, making a comparison between outputs and expected values, measuring signal characteristics, and the like.
2. Description of the Background Art
Semiconductor devices undergo various tests in respect of reliabilities. There are two types of tests for the semiconductor devices: a DC/AC characteristic test for measuring direct current (DC) characteristics such as currents or voltages of respective terminals and alternate current (AC) characteristics such as operation frequency and operation timing of the devices; and a functional test (verification) for determining whether or not the semiconductor devices function as designed.
In the DC characteristic test, such characteristics as inputs, outputs, input-to-output transmission, a total current and power consumption are measured. In the AC characteristic test, rising times and falling times of waveforms of input signals and output signals, a delay time in propagation between input and output terminals, a set-up time, a hold time, a minimum clock pulse width, an operation frequency and the like are measured.
The functional test is a test for checking if semiconductor devices operate without indicating any abnormality in its function, when the semiconductor devices have prescribed operating conditions imposed thereon. The functional test is usually carried out by comparing and checking a pattern applied to an output terminal with an expected pattern when a test pattern is applied to an input terminal.
FIG. 1 is a conceptional diagram of functional test of a semiconductor device, particularly a semiconductor integrated circuit device. Referring to FIG. 1, a testing apparatus includes a pattern generator 500 for generating a test pattern, a test pattern applying apparatus 501 for receiving the test pattern from pattern generator 500, to convert the received test pattern into logic signals of logical one or logical zero and apply the signals to an input terminal 510 of a device 502 under test, an output pattern discriminating circuit 504 for receiving an output signal from device 502 under test to convert the received output signal into a logic signal, an expected pattern storing circuit 505 for storing therein expected values of an output pattern corresponding to an input test pattern generated by pattern generator 500, a comparison circuit 506 for making a comparison between an output of output pattern discriminating circuit 504 and an output of expected pattern storing circuit 505, and a determining circuit 507 for determining whether device 502 operates normally, in response to an output of comparison circuit 506.
A power supply pin terminal of device 502 is supplied with a predetermined operating supply voltage from a power supply 503, and a ground terminal of device 502 is connected to a ground potential GND. Various methods for realizing such functional test of semiconductor device have been considered. With regard to generation of a test pattern also, a method for most efficiently creating a test pattern having higher test coverage is considered.
FIG. 2 is a diagram showing one example of a conventional testing method of a semiconductor device and conceptionally showing a test pattern storing method. Referring to FIG. 2, a testing system includes a test pattern generator 550 comprised such as of a logic simulator, and a testing apparatus 551 for receiving an input test pattern and an expected output pattern from test pattern generator 550, applying the input test pattern to a device 560 under measurement and comparing an output response pattern from device 560 with the received expected output pattern, thereby determining pass/fail of device 560.
Testing apparatus 551 includes a memory 555 for storing the input test pattern therein, a memory 556 for storing the expected output pattern from test pattern generator 550, and a comparator 557 for making a comparison between the output response pattern from device 560 and the expected output pattern of memory 556.
In the testing method called the test pattern storing method, an input test pattern and an expected output pattern are created in advance by test pattern generator 550. These input test pattern and expected output pattern are stored in memories 555 and 556 in testing apparatus 551 such as an LSI tester. The input test pattern of memory 555 is applied to device 560 in testing. Device 560 carries out a certain operation in accordance with the applied input test pattern and outputs an output signal indicating results of the operation as an output response pattern. Comparator 557 included in testing apparatus 551 compares the output response pattern from device 560 with the expected output pattern stored in memory 556. If this expected output pattern matches the output response pattern, then it is determined that device 560 operates normally. Conversely, if the expected output pattern mismatches the output response pattern, then it determined that there is a failure in device 560. Analyzing the input test pattern generated by test pattern generator 550 also allows a fault diagnosis (an analysis of the failure, or the like).
In such a testing apparatus, a card (board) which is called pin electronics for applying a signal directly to a device under measurement and receiving the signal therefrom is installed in a test head, one for each pin terminal of a semiconductor device under measurement. The pin electronics is employed not only in a functional testing of a semiconductor device but also in a DC/AC characteristic testing.
FIG. 3 is a diagram showing a schematic structure of a general pin electronics circuit incorporated in a semiconductor testing apparatus. Referring to FIG. 3, a pin electronics circuit 200 includes a driver 201 for applying a voltage waveform to a semiconductor device 206 under test (hereinafter referred to simply as LSI) in accordance with a test pattern, and a comparator 202 for receiving an output signal from the LSI to determine whether a logical value of the received output signal is logical one or logical zero. Pin electronics circuit 200 further includes a switching element 205a for connecting an output of driver 201 to a node 208, and a switching element 205b for connecting the node 208 and an input of comparator 202. One of switching elements 205a and 205b is rendered conductive by a control signal from a control circuit not shown. Node 208 of pin electronics circuit 200 is connected via a transmission line 203 to a terminal 207 of LSI 206. Terminal 207 may be either a signal output terminal or a signal input terminal, or alternatively, a terminal for both inputting and outputting a signal.
Pin electronics circuit 200 further includes a resistor 204 connected via a switching element 205c to node 208. When there is a mismatch between output resistance of an output buffer of LSI 206 and characteristic impedance of transmission line 203, reflection accompanied by undershoot and overshoot is produced in signal waveforms at node 208. In order to inhibit such reflection, resistor 204 is provided as terminating resistance. An operation will now be described.
When pin terminal 207 of LSI 206 is a signal input terminal, only switching element 205a included in pin electronics circuit 200 is turned on in response to an output of the control circuit not shown, so as to connect the output of driver 201 to node 208. A voltage signal in accordance with a test pattern is applied to an input of driver 201. Driver 201 applies a voltage waveform in accordance with this test pattern via node 208 and transmission line 203 to pin terminal 207 of LSI 206. LSI 206 operates in accordance with the voltage signal applied to pin terminal 207.
When pin terminal 207 of LSI 206 is a signal output terminal, only switching element 205b included in pin electronics circuit 200 is turned on. Comparator 202 receives an output signal from pin terminal 207 of LSI 206 via transmission line 203, to convert the received output signal into a signal of logical one or logical zero. Comparator 202 is supplied with an expected output voltage (VOH, VOL) of LSI 206 as a reference value. Based on the applied expected output voltage, comparator 202 discriminates the logic level of the output signal from LSI 206. The logic signal generated by comparator 202 is compared with an expected output pattern. Pass/fail of LSI 206 is determined in accordance with the result of the comparison.
Transmission line 203 has impedance. LSI 206 includes an output buffer circuit as shown in FIG. 4 at its output portion.
FIG. 4 is a diagram showing structure of an output stage of LSI 206. Referring to FIG. 4, LSI 206 includes an internal circuit 250 for performing a predetermined function, and an output buffer circuit 251 for buffering an output signal from internal circuit 250 to transmit the buffered output signal to pin terminal 207. Output buffer circuit 251 includes a p channel MOS (insulated gate type) transistor PT and an n channel MOS transistor NT that are complementary-connected between an operating supply potential Vcc and another supply potential Vss. Transistors PT and NT include a resistance component (ON resistance) R that exists when these transistors are in an ON state.
Output resistance of output buffer circuit 251 contributes as output impedance at pin terminal 207 of LSI 206. When there is a mismatch between the output impedance at pin terminal 207 of LSI 206 and impedance on transmission line 203, reflection of a signal occurs on node 208, so that overshoot and undershoot are generated in this signal. Further, even if the output impedance at pin terminal 207 of LSI 206 matches the impedance on transmission line 203 and hence no reflection occurs, stray capacitance and parasitic inductance exist on transmission line 203, resulting in a ringing of a signal on node 208. In order to inhibit such signal reflection and ringing, when pin terminal 207 is a signal output terminal, switching element 205c as well as switching element 205b is turned on, so that resistor 204 is connected as terminating resistance to node 208. A brief description will now be given on function of terminating resistance 204.
FIG. 5 is a diagram showing a connection in a case in which the transmission line system is unterminating. Referring to FIG. 5, pin terminal 207 of LSI 206 is connected via transmission line 203 to comparator 202. In the connection shown in FIG. 5, when the output impedance (output resistance) at pin terminal 207 is lower than the characteristic impedance of the transmission line, the undershoot and overshoot of a signal is generated on input node 208 of comparator 202. More specifically, comparator 202 has high input impedance, and a voltage signal that is transmitted from pin terminal 207 via transmission line 203 to node 208 undergoes a total reflection at an input terminal of comparator 202. The following relation is obtained: EQU Vc=2.multidot.Z0.multidot.V/(Z+Z0)
where the output impedance (output resistance) of pin terminal 207 is Z, the characteristic impedance of transmission line 203 is Z, the output voltage applied to pin terminal 207 is V, and a voltage on node 208 is Vc.
If output impedance Z of pin terminal 207 is lower than characteristic impedance Z0 of transmission line 203, Vc&gt;V is satisfied. That is, the amplitude of the voltage signal on input node 208 of comparator 202 becomes larger than that of the voltage signal at pin terminal 207, so that the undershoot and overshoot of the voltage signal is generated at input node 208. The manner in which the undershoot is generated at node 208 is shown in FIG. 6.
FIG. 6 is a diagram schematically showing a signal waveform obtained when the undershoot is generated at input node 208 of comparator 202. Referring to FIG. 6, a logical high level of an output signal from pin terminal 207 indicates 5 V, while a logical low level of the output signal indicates 0 V. When undershoot occurs in this voltage signal waveform 209, the undershoot causes noise, thereby failing to convert the output signal into a correct logic signal in comparator 202. In addition, when AC characteristics such as a falling time and a rising time of the output signal waveform of LSI 206 are measured, timing errors occur, thereby failing to make an accurate measurement. For accurate measurement in functional testing of LSI 206 under such conditions, it is necessary to measure a signal in the state where ringing is smoothed over, thereby failing to carry out a fast functional verification.
As a method for inhibiting the overshoot, undershoot and ringing caused by reflection at node 208, resistive termination is employed. In the resistive termination, switching element 205c shown in FIG. 3 is turned on, so that resistor 204 is connected between node 208 and potential Vss.
FIG. 7 is a diagram showing a connection configuration of pin electronics and LSI in the use of the resistive termination. Referring to FIG. 7, resistor 204 is connected between node 208 and supply potential Vss (normally ground potential 0 V). Assume that a resistance value of resistor 204 is RT. At pin terminal 207 of LSI 206, there exists output resistance R due to ON resistance of transistors PT and NT included in output buffer circuit 251 shown in FIG. 4. Only ON resistance R of p channel MOS transistor PT (see FIG. 4) connected to operating supply potential Vcc is shown in FIG. 7.
FIG. 8 is a diagram showing a voltage waveform on node 208 in the use of the resistive termination. Distorted pulse waveform 209 (see FIG. 6) on node 208 in the case where no resistive termination is carried out is shown as well in FIG. 8. When the logical level of a signal appearing at pin terminal 207 is logical one, a voltage detected by comparator 202 (a voltage on node 208) is obtained by the following relation: EQU Vcc.multidot.RT/(R+RT)
where a direct current resistance component of transmission line 203 is ignored. As described above, the voltage applied to node 208 is divided by terminating the transmission line by using resistor 204, whereby the generation of undershoot, overshoot and ringing on node 208 can be inhibited.
As apparent from FIG. 8, a voltage waveform 210 on input node 208 of comparator 202, obtained in the resistive termination using resistor 204 is a very smooth waveform as compared to signal waveform 209 on node 208 to which no terminating resistance is connected.
If such resistor 204 is connected to node 208, a current flowing through resistor 204 is obtained by the relation Vcc/(R+RT) when the logical level of an output of LSI 206 is logical one.
When LSI 206 outputs a signal of logical zero to pin terminal 207, n channel MOS transistor NT shown in FIG. 4 is turned on, whereas p channel MOS transistor PT is turned off. This results in such a state that resistor R shown in FIG. 7 is connected to potential Vss (0 V), the voltage on node 208 is Vss (0 V), and the current flowing through resistor 204 is also 0 mA.
A general review of pin electronics is given in "MODERN ATE" by M. R. Barber et al., IEEE DESIGN & TEST April 1987, pp. 23-30.
The use of resistive termination to reduce signal ringing caused by impedance mismatching of a general transmission line is described in "Correct Signal Faults by Implementing Line-analysis Theory" by D. Royle, EDN Jun. 23, 1988, pp. 143 to 148.
A solution for the undershoot/overshoot problem in pin electronics by providing a series resistor on a transmission line is described in "Timing Measurements on CMOS VLSI DEVICES DESIGNED TO DRIVE TTL LOADS" by M. R. Barber et al., 1986 International Test Conference, IEEE, Paper 4.4, pp. 161-168.
In the conventional resistive termination used as a method for inhibiting the generation of overshoot, undershoot and ringing, a current flows through terminating resistance 204 when the logical level of an output of LSI 206 is logical one. This current is supplied via an output transistor from a power supply line of output buffer circuit 251 (see FIG. 4) in LSI 206. This allows an excess current to flow into LSI 206, causing an electromigration problem in an internal interconnection of LSI 206, resulting in a degradation in reliability of LSI 206.
In addition, connecting the resistor 204 to node 208 causes an increase in RC delay on the transmission line and an increase in the rising time and the falling time of the signal waveform on node 208, i.e., an increase in time constant, whereby the output signal waveform is rounded. When the output signal waveform is rounded in this manner, such a problem occurs that even if LSI 206 is operated at an actual operation clock frequency, an accurate output signal cannot be obtained at predetermined timing, and hence no accurate functional testing can be made. Further, another problem arises that no precise measurement can be made in DC/AC characteristic measurements. When a functional testing is carried out with a deviation in measurement timing in consideration of the rounding of the output signal waveform, a fast functional testing for the LSI cannot be carried out, resulting in a longer test time. This problem becomes a greater problem as the LSI operates faster and/or requires a larger number of pin terminals.